1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of controlling the same, and more particularly to a refresh control for a semiconductor memory device having a mode in which one bit of data is stored by two memory cells.
2. Description of Related Art
It is proposed a method that retains one bit data by using twin memory cell. FIG. 14 is a diagram for explaining such a method. Referring to FIG. 14, a cell array 11 a bit line pair comprising first and second bit lines B and /B which are commonly connected to a sense amplifier (SA) 12, and is provided with a first memory cell MC1 which is connected to a first word line WL1 and the first bit line B, and a second memory cell MC2 which is connected to a second word line WL2 and the second bit line /B. In a normal mode (normal operation) of one bit-one cell, the first and second word lines WL1 and WL2 which are respectively driven by first and second word drivers WD1 and WD2, are assigned separate addresses, and different data are written into the first and second memory cells and read out separately. One the other hand, in a partial mode (also referred to as a “twin cell mode”) such as in a stand-by state or the like, in which low power consumption is achieved, the first and second word lines WL1 and WL2 are assigned the same address and are driven by the first and second word drivers WD1 and WD2 at a high voltage with the same timing. At the time of entering the partial mode switched from the normal mode, the data in the first memory cell MC1, for example, is copied and saved into the second memory cell MC2, whereby the one-bit information is stored into two memory cells complimentarily. With such a configuration, hold characteristics of dynamic type cells improve, and it is made possible to remarkably lengthen the interval of the refresh operation, which is performed periodically, in comparison with the case of one bit/one cell. As a consequence, current consumption resulting from the refresh operation is reduced, and reduction in current consumption is achieved during a stand-by state.
Recently, a semiconductor memory device known as “pseudo SRAM” has been developed that has the same specifications as SRAM (static random access memory) when observed from outside, though it uses the same memory cells as those employed in DRAM. Having both advantages of SRAM and DRAM, it is recognized as suitable for portable devices or the like. Unlike DRAM, the pseudo SRAM does not need to be provided with row addresses and column addresses separately, and for this reason, it does not require timing signals such as RAS and CAS. As in general-purpose SRAMs, it is sufficient for the pseudo SRAM to be provided with addresses at one time, and it performs read/write operations by fetching addresses inside using a chip enable signal, which corresponds to clock in clock synchronous type semiconductor memory devices, as a trigger. In addition, it has been known that an asynchronous pseudo SRAM that does not require external refresh control so that it can operate with completely the same specifications as those of general-purpose SRAMs, suffers from such problems that normal access is affected by refresh operations and that refresh operations become impossible by continuous write operations. With an aim of resolving these problems, the inventors of the present application have already proposed a semiconductor memory device in which after refreshing a memory cell corresponding to a refresh address signal in response to an address change-detecting signal generated in response to an input address signal, the memory cell corresponding to the input address signal is accessed (for example, see Patent Document 1 listed below). In pseudo SRAMs, the refresh time is set in an internal between normal operations, and the pulse widths necessary for the refresh operation cannot be widened. This is because it leads to degradations in access time and cycle characteristics. Also, even in DRAMs compatible with asynchronous SRAMs in which read/write operations are performed after refreshing as described in the above-mentioned Patent Document 1, it is undesirable to widen the refresh operations since it causes degradation in access time. Moreover, in terms of performance specifications, it is difficult to widen the time for the refresh operations in a cell array of high-speed synchronous SRAM that is to be incorporated in portable terminals and switching functions and routing functions for networks.
In the twin cell DRAM shown in FIG. 14, at the switching from the normal mode to the partial mode, when data in the first memory cell are saved in the second memory cell, the data in the two memory cells may collide with each other and be damaged if the first and second word lines WL1 and WL2 are selected at the same time as shown in FIG. 15A. Specifically, referring to FIG. 14, in the partial mode, the first memory cell MC1 and the second memory cell MC2 that together form a twin cell store one bit of data complimentarily. In the case where both the first and second memory cells store data HIGH in the normal mode, if the first and second word lines WL1 and WL2 are simultaneously selected at the time of switching to the partial mode in order to read out the cell data in the first memory cell MC1 and write it into the second memory cell MC2, both the first and second memory cells drive the complementary bit line pair B, /B with voltage HIGH; therefore, the differential voltage between the bit line pair B, /B does not widen. Consequently, if the differential voltage between the bit line pair is differential amplified by the sense amplifier 12 and rewritten into the first and second memory cells, the data of the first and second memory cells are destroyed.
In addition, the refresh period extends if the configuration is adopted in which, as shown in FIG. 15B, the first word line WL1 is selected (pulse width t0 is equal to the pulse width of the word line in the normal mode) to restore (write back) the first memory cell MC1 by the sense amplifier 12's reading and thereafter the second word line WL2 is selected to write the cell data of the first memory cell MC1 into the second memory cell MC2. Specifically, read/write (READ/WRITE) access is suspended until the refresh operation ends. When a memory that is compliant to SRAM interface such as the above-described pseudo SRAM or the like does not have an external terminal for exchanging a refresh control signal with an external controller, it is necessary to carry out timing design in advance so that READ/WRITE operations are performed after the refresh operation finishes, and consequently, access time increases.
It is also known that there is a semiconductor memory device that switches from a state wherein data are held with one bit/one cell in a normal mode to a twin cell mode wherein information is held with one bit/two cells, and in the twin cell mode, two sub-word lines are simultaneously brought into a selected state to read out stored data in the memory cell with bit lines that form a pair and to perform a sense operation (for example, see Patent Document 2 listed below). In Patent Document 2 (FIG. 10), for example, as shown in FIG. 16 appended to the present application, a sub-word line SWLL<0> is driven (activated) to a selected state and a data of the cell connected to the sub-word line SWLL<0> is read out on the corresponding bit line (in FIG. 16, a HIGH level data is read out), but, because the other bit line is not connected to the memory cell, its read voltage ΔV2=0 and the precharge voltage level is maintained. Subsequently, sense amplifier-activating signals SON and ZSOP (corresponding to the sense enable signal SE in FIG. 14) are activated, so that a data stored in one memory cell is detected and amplified by a sense amplifier and is latched. After the sense operation is completed and the bit line potential is driven to an array power supply voltage VCCS and a ground voltage level, a sub-word line SWLR<1>, which is the other one of the pair, is driven to a selected state. The memory cell connected to the sub-word line SWLR<1> stores the data that has been amplified by the sense amplifier and latched. In other words, a cell 1 and a cell 2, which are connected to the sub-word lines SWLL<0> and SWLR<1>, store complimentary data. After a predetermined time has elapsed, the sub-word lines SWLL<0> and SWLR<1> are driven to a non-selected state and the sense amplifier-activating signals SON and ZSOP are inactivated, whereby the data in the cell 1 is moved to the cell 2, thus completing a data write operation to a unit cell in the twin cell mode. The cell data write operation is similar to the method shown in FIG. 15B.
Also known as a semiconductor memory device having one bit/one cell and one bit/two cells modes is, for example, a configuration in which two cells are connected to the same bit line (for example, see Patent Document 3 below). Also known is a semiconductor memory device in which data in two cells in a twin cell mode have a complementary relationship, the two cells are connected to the same word line, and switching to one bit/one data is not performed (for example, see Patent Document 4 below).
With regard to a configuration in which an intermediate voltage is written into a dynamic type memory cell, which will be described in Detailed Description of the Preferred Embodiments hereinbelow, also further known is a configuration that adopts a system in which a bit line pair is precharged to ½VBLH to activate a dummy word line so that ½VBLH is written into a dummy cell having the same structure and capacity as those of normal memory cells (for example, see Patent Document 5 below)
[Patent Document 1]
Japanese Unexamined Patent Publication No. 2002-74944 (see p. 8 and FIG. 1).
[Patent Document 2]
Japanese Unexamined Patent Publication No. 2002-170386 (see p. 20 and FIG. 10).
[Patent Document 3]
Japanese Unexamined Patent Publication No. 2000-057763 (see p. 4 and FIG. 4).
[Patent Document 4]
Japanese Unexamined Patent Publication No. 2001-143463 (see pp. 3-4 and FIG. 1).
[Patent Document 5]
Japanese Unexamined Patent Publication No. 2001-307479 (see p. 4 and FIG. 10).